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Abstract

Matrix–matrix multiplication plays an important role in numerical linear algebra (finite element method, dynamical-system stability analysis, principal component analysis, data compression) and deep learning (batch processing, im2col-based convolution, and transformer attention). Moreover, all Level-3 BLAS operations rely on the GEMM kernel, which makes the development of high-performance matrix-multiplication algorithms a highly relevant task. This study evaluates the attainable single-threaded performance of square-matrix multiplication using SSE and AVX instructions on modern x86 processors. It investigates how the algorithm, cache-blocking strategy, horizontal operations, and loop-unrolling depth affect performance. Three matrix multiplication algorithms are examined: classical, column-buffered, and block-based, each implemented with and without horizontal operations. For every algorithm, versions with loop unrolling by 4 and 8 iterations are developed. Performance measurements are conducted on four processors (AMD Ryzen 7 3800X, AMD Ryzen 7 7700, Intel Core i5-12400, Intel Core Ultra 7 265K) with thread affinity set to a single core. The results show that, for SSE implementations on modern processors, eliminating horizontal operations does not improve performance, contrary to previously published findings. For AVX implementations, however, removing horizontal operations yields a significant speedup: peak performance reached 97.1 GFLOPS, which is 1.61 times higher than the variant with horizontal operations. Column-buffered multiplication achieved the highest peak performance but suffers a substantial performance degradation at large matrix sizes. Block-based multiplication provides more consistent results. The effectiveness of optimizations depends significantly on the instruction set used and the specific processor model. The choice of algorithm and loop-unrolling parameters should account for both problem size and the target platform's characteristics. Future work includes multithreaded implementation and investigating methods to reduce the performance degradation of column-buffered multiplication.

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